Combinational Circuit


Q11.

If there are m input lines and n output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of m+n is ________ .
GateOverflow

Q12.

The circuit given in the figure below is
GateOverflow

Q13.

Which one of the following circuits implements the Boolean function given below?f(x,y,z) = m_0+m_1+m_3+m_4+m_5+m_6where m_i is the i^{th} minterm.
GateOverflow

Q14.

A Boolean digital circuit is composed using two 4-input multiplexers (M1 and M2) and one 2-input multiplexer (M3) as shown in the figure. X0-X7 are the inputs of the multiplexers M1 and M2 and could be connected to either 0 or 1. The select lines of the multiplexers are connected to Boolean variables A, B and C as shown.Which one of the following set of values of (X0, X1, X2, X3, X4, X5, X6, X7) will realise the Boolean function \bar{A}+\bar{A}\cdot \bar{C}+A\cdot \bar{B}\cdot C ?
GateOverflow

Q15.

When two 8-bit numbers A_{7}....A_{0} and B_{7}....B_{0} in 2's complement representation (with A_{0} and B_{0} as the least significant bits ) are added using a ripple-carry Combinational Circuit, the sum bits obtained are S_{7}....S_{0} and the carry bits are C_{7}....C_{0}. An overflow is said to have occurred if
GateOverflow

Q16.

If half adders and full adders are implements using gates, then for the addition of two 17 bit numbers (using minimum gates) the number of half adders and full adders required will be
GateOverflow

Q17.

Consider the two cascaded 2-to-1 multiplexers as shown in the figure. The minimal sum of products form of the output X is
GateOverflow

Q18.

Consider the following combinational function block involving four Boolean variables x, y, a, b where x, a, b are inputs and y is the output. f (x, y, a, b) { if (x is 1) y = a; else y = b; } Which one of the following digital logic blocks is the most suitable for implementing this function?
GateOverflow

Q19.

The logic circuit given below converts a binary code y1, y2, y3 into
GateOverflow

Q20.

How many programmable fuses are required in a PLA which takes 16 inputs and gives 8 outputs? It has to use 8 OR gates and 32 AND gates.
GateOverflow