GATE PYQ

Combinational Circuit

Q11.
The logic circuit given below converts a binary code y1, y2, y3 into

Q12.
The output of a 2-input multiplexer is connected back to one of its inputs as shown in the figure.Match the functional equivalence of this circuit to one of the following options.

Q13.
For a binary half-subtractor having two inputs A and B, the correct set of logical outputs D(=A minus B) and X(=borrow) are

Q14.
In the following truth table, V = 1 if and only if the input is valid. What function does the truth table represent?

Q15.
When two 8-bit numbers A_{7}....A_{0} and B_{7}....B_{0} in 2's complement representation (with A_{0} and B_{0} as the least significant bits ) are added using a ripple-carry Combinational Circuit, the sum bits obtained are S_{7}....S_{0} and the carry bits are C_{7}....C_{0}. An overflow is said to have occurred if

Q16.
Consider the two cascaded 2-to-1 multiplexers as shown in the figure. The minimal sum of products form of the output X is

Q17.
A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The number of select lines needed for the multiplexer is ______.

Q18.
The logic operations of two combinational circuits in Figure-I and Figure -II are

Q19.
If half adders and full adders are implements using gates, then for the addition of two 17 bit numbers (using minimum gates) the number of half adders and full adders required will be

Q20.
How many programmable fuses are required in a PLA which takes 16 inputs and gives 8 outputs? It has to use 8 OR gates and 32 AND gates.